Ethernet, SATA and PCIe debugging for IoT devices

Article by: Teledyne LeCroy

As part of the ongoing review of serial data debugging standards for IoT devices, this article examines three protocols: Ethernet, SATA, and PCIe.

In our ongoing review of debugging serial data standards for Internet of Things (IoT) devices (Part 1 here), let’s now move on to three more popular protocols: Ethernet, SATA, and PCIe. Ethernet is found in computer networking applications, while Serial Advanced Technology Attachment (SATA) connects host bus adapters to mass storage devices. The Peripheral Component Interconnect Express (PCI Express or PCIe) handles the communication between root complexes (motherboards) and expansion card interfaces.

Figure 1: A generic IoT block diagram shows serial data links in blue.

Figure 2 shows an oscilloscope screenshot of an actual example; here we are trying to narrow down a SATA digital encoder issue related to spread spectrum clock (SSC). On the right side is an eye diagram of the SSC which was extracted from the data stream. This signal, displayed in the Channel 2 tab through the use of an SSC track demodulator, has a step function resulting from very abrupt changes in the SSC modulation. This waveform turned out to be the cause of the encoder problem. The SSC function should look like the one on the left in the Lane 1 tab, with a smoother triangular waveform.

Figure 2: An SSC track demodulator helped diagnose the digital encoder problem in this SATA SSC signal.

The ability to simultaneously examine the protocol view and the physical layer is a valuable tool for debugging IoT serial data functionality. The screenshot in Figure 3 shows a PCIe signal acquisition on the left with the protocol analysis view on the right. Touching any point in the Protocol Analyzer view will link to that same point in time in the waveform. Note that while Figure 3 shows an example x1 link, Teledyne LeCroy’s ProtoSync software option currently supports simultaneous physical layer waveform views, decode annotation overlays, and analysis views protocol for PCIe lane/direction combinations of 1×1, 1×2, and 4×1 for all PCIe generations up to 4.0.

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If the Protocol Analyzer displays a protocol error, touching this item takes you to the exact location where the error occurred in the acquisition waveform. Perhaps the cause is a non-monotonic edge or a rise time slow enough to have been misinterpreted. It could be a glitch, misfire, or ringing. But whatever the cause, time-correlated waveform and protocol views will isolate the problem.

Figure 3: Time-correlated waveform and protocol views help identify problem areas in a PCIe serial data stream.

In another debug example of the PCIe protocol, the IoT device was mistakenly sending an Electrical Standby Output Ordered Set (EIEOS) link layer message at regular intervals. An EIEOS is part of a PCIe channel’s power management protocol, instructing the channel to exit the L0 sleep state and return to the L0 state. In Figure 4, these messages appear in the top left acquisition waveform as red striped items, one of which appears in the center left zoom trace. The protocol analyzer tells us that there were 84 instances of the EIEOS packet being sent.

Figure 4: A device malfunction is identified here at the PCIe protocol layer.

Similarly, time-correlated waveform and protocol views can help monitor Ethernet traffic, such as video signals from a security camera. Another important tool for Ethernet debugging is the conformance mask test.

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