Renesas has introduced the industry’s first line of clock buffers and multiplexers that meet stringent PCIe 6.0 specifications. The new devices will allow companies to build motherboards and other devices that must meet PCIe 6.0 requirements for performance and signal integrity, but are also compatible with PCIe 5.0 applications.
Renesas adds 11 new RC190xx clock buffers and four new RC192xx multiplexers that have additive jitter of just 4fs RMS, which is virtually silent, an extremely important feature for PCIe Gen6 applications. Additionally, the new clock buffers feature 1.4 ns input-output delay, 35 ps output lag, and -80 dB power supply rejection ratio (PSRR) at 100 kHz. The new chips complement Renesas’ 9SQ440, 9FGV1002 and 9FGV1006 low-jitter clock generators and enable the company to offer a complete PCIe 6.0 timing solution.
256 Gbps bi-directional bandwidth on a 16-lane interface or 64 Gbps bi-directional bandwidth on a 4-lane interface will soon no longer be required for consumer graphics cards or solid-state drives. But in the data center, bandwidth is everything. Meanwhile, ultra-complex PCIe Gen 6 circuit design and testing will take time, so the earlier hardware developers start creating new products, the better. This could allow developers of next-generation server platforms to start designing motherboards, accelerators, network cards, and SSDs.
“By providing the first discrete timing solution for PCIe Gen 6, Renesas is enabling customers to develop the next generation of high-performance systems,” said Rich Wawrzyniak, principal analyst for Semico Research in a Renesas release. “It will be interesting to see the innovative implementations that will result from this new capability, especially considering how solutions for the emerging chip market are beginning to evolve, with the need for increased speed and bandwidth a constant. underlying.”
To increase the total bandwidth of a 16-lane PCIe slot to 256 Gbps in both directions, the PCIe Gen 6 specification increases the data transfer rate to 64 Gbps and adopts amplitude modulation of pulse with four levels (PAM-4) signaling together forward. error correction (FEC). A very high data transfer rate and a new signal encoding method not only require further logical enhancements to the specification (e.g. further improved FEC with CRC), but also increase the clock signal quality requirements – Clock jitter performance of a PCIe Gen 6 subsystem should be less than 100fs RMS. This is where the brand new clock buffers (also called clock drivers) and multiplexers come into play.
The operation of a circuit must be synchronized, but sometimes the clock signal from the same source arrives at different registers at different times due to different path lengths between two clock paths, or due to clocks closed or wavy. This phenomenon is called clock skew or timing skew and can cause hold time violation errors. Clock buffers allow clocks to be distributed synchronously and efficiently by preserving the clock properties of the input signal, and minimizing additive jitter noise is especially important for PCIe 6.0 subsystems.
A multiplexer is basically a multiple input, single output switch used for signal distribution. Since we are dealing with a data transfer rate of 64 GTps, the MUXs have to handle this signal rate and guarantee clean signals, which is why brand new multiplexers for PCIe Gen 6 applications are needed.
“PCIe Gen6 synchronization will be at the heart of new equipment in data centers, high-speed networks and other applications,” said Zaher Baidas, vice president of synchronization products division at Renesas. “As we have done with previous generations, Renesas provides our customers with the first synchronization solution to enable these new, higher performance systems. Our customers know that we have the technical expertise and market knowledge to ensure that their products will be able to meet future requirements as well.”